A key requirement of digital computers is the ability to use logic functions to perform arithmetic operations. the basis of this is addition if we can add two binary numbers, we can just as easily subtract them , or get a little fancier and perform multiplication two possible values, 0, 1 there are only four possible combinations of inputs. these four possibilities , and the resulting sums, are
the fourth line indicate that we have to account for two output bits when we add two input bits: the sum and a possible carry . Let's set up as truth table with two inputs, and see where we can go from there.
well , this looks familiar, doesn't it? the carry output is a simple AND function, and the sum is an Exclusive-OR . thus, we can use two gate to add these two bits together .
Ok , we've got a good start on this circuit . however, we're nor done yet. in a computer, we'll have to add multi-bit numbers to gather. if each pair of bits can produce an output carry , it must also be able to recognize and include a carry from the next lower order of magnitude. this is the same requirement as adding decimal number - if you have a carry from one column to the next , the next column has to include that carry . we have to do the same thing with binary numbers, for the same reason.as a result, the circuit to the left is known as a "half adder," because it only does half of the job . we need a circuit that will do the entire job.
to construct a full adder circuit, we'll need there inputs and two outputs. since we'll have both an input carry and an output carry, we'll designate them as C and C . At the same time, we;ll use S to designate the final sum output. the resulting truth table is shown below. the resulting full adder circuit is shown below.
positive edge - triggered (without bubble at clock input) :input) S-R , and D negative edge - triggered(with bubble at clock input):S-R, J-K and D
THE s-r, j-k AND d inputs are called synchronous inputs because data on these inputs transferred to the flip-flop's output only on the triggering edge of the clock pulse. on the other hand, the direct set and clear inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock.for the synchronous operations to work properly, these synchronous inputs must both be kept LOW.
the fourth line indicate that we have to account for two output bits when we add two input bits: the sum and a possible carry . Let's set up as truth table with two inputs, and see where we can go from there.
well , this looks familiar, doesn't it? the carry output is a simple AND function, and the sum is an Exclusive-OR . thus, we can use two gate to add these two bits together .
Ok , we've got a good start on this circuit . however, we're nor done yet. in a computer, we'll have to add multi-bit numbers to gather. if each pair of bits can produce an output carry , it must also be able to recognize and include a carry from the next lower order of magnitude. this is the same requirement as adding decimal number - if you have a carry from one column to the next , the next column has to include that carry . we have to do the same thing with binary numbers, for the same reason.as a result, the circuit to the left is known as a "half adder," because it only does half of the job . we need a circuit that will do the entire job.
to construct a full adder circuit, we'll need there inputs and two outputs. since we'll have both an input carry and an output carry, we'll designate them as C and C . At the same time, we;ll use S to designate the final sum output. the resulting truth table is shown below. the resulting full adder circuit is shown below.
Negative numbers and binary subtraction
We have seen how simple logic gate can perform the process of binary addition . It is only logical to assume that a similar circuit could perform binary subtraction. if we look at the possibilities involved subtracting one 1-bit number from another , we can quickly that three of the four possible combinations are easy and straight-forward. the fourth one involves a bit more:
that borrow bit is just like a borrow in decimal subtraction: it subtracts from the next higher order of magnitude in the overall number. Let's what the truth table looks like. this is an interesting result. the difference, A-B, is still an Exclusive-OR function, just as the sum was for addition. the borrow is still an AND function, but is A'B instead of AB
What we'd like to do, now, is an easy way to use the binary adder to perform subtraction as well. we already have half of it working: The difference invert the sense of the exclusive-OR function.
What would be really nice is to convert B to the negative equivalent of its value., and then use the basic adder just as it stand. Now that we have an easy way to obtain the negative of any number, we can convert our original 4-bit adder circuit to an adder/subtractor. leaving the inputs unchanged, we get the result of A+B but if we invert B and add 1 with low -order CIN, we get the result of A-B
What we'd like to do, now, is an easy way to use the binary adder to perform subtraction as well. we already have half of it working: The difference invert the sense of the exclusive-OR function.
What would be really nice is to convert B to the negative equivalent of its value., and then use the basic adder just as it stand. Now that we have an easy way to obtain the negative of any number, we can convert our original 4-bit adder circuit to an adder/subtractor. leaving the inputs unchanged, we get the result of A+B but if we invert B and add 1 with low -order CIN, we get the result of A-B
Flip Flops
The flip-flop is a circuit providing one bit memory . flip-flops are synchronous bistable devices. the term synchronous means the output changes state only when the clock input is triggered. that is , changes in the output occur in synchronization with the clock.
A flip-flop is triggered by a clock signal due to which the synchronous data inputs enter the flip-flop. A flip flop has two outputs Q and Q' which are complementary to each other . when the flip - flop is set , Q will be high and Q' will be low . when the flip flop is at rest Q will be low and Q' will be high. when the flip-flop is triggered by the clock input, the flip-flop may remain unaffected or change over to the opposite state , depending on the synchronous data inputs
flip- flop is a kind of multivibrator. there are three types of multivibrators:
- monostable multivibrator (also called one-shot) has only one stable state . it produces a single pulse in response to a triggering input.
- bistable multivibrator exhibits two stable states. it is able to retain the two SET and RESET states indefinitely. it is commonly used as a basic building block for counters, register and memories.
- A stable multivibrator has no stable state at all . it is used primarily as an oscillator to generate periodic pulse waveforms for timing purposes
positive edge - triggered (without bubble at clock input) :input) S-R , and D negative edge - triggered(with bubble at clock input):S-R, J-K and D
THE s-r, j-k AND d inputs are called synchronous inputs because data on these inputs transferred to the flip-flop's output only on the triggering edge of the clock pulse. on the other hand, the direct set and clear inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock.for the synchronous operations to work properly, these synchronous inputs must both be kept LOW.
Edge-triggered S-R flip-flop
the basic operation is illustrated below , along with the truth table for this type of flip-flop. the operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge.
As S=1, R=0. Flip-Flop SETS on the rising clock edge
Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock)without affecting the output. this is illustrated in the timing diagram below:
Edge-triggered J-K flip-flop
the J-K flip-flop works very similar to S-R flip-flop. the only difference is that this flip-flop has NO invalid state. the outputs toggle (change to the opposite state) when both and K inputs are HIGH. the truth table is shown below.
Edge-triggered J-K flip-flop
The operations of a D flip-flop is much more simple. it has only one input addition to the clock. it is very useful when a single data bit is to be stored . if there is a HIGH on the D input when a clock pulse is applied , the flip-flop SET s and stores a1. if there is a LOW on the D input when a clock pulse is applied , the flip-flop RESET s and stores a 0. the truth table below summarize the operations of the positive edge-triggered D FLIP-FLOP.
As before , the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.
Pulse-Triggered(Master-Slave) Flip-Flop
The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock pulse but the output does not reflect the input state unit the falling edge of the clock pulse. As this kind of flip-flops are sensitive to any change of the input levels during the clock pulse is still HIGH , the inputs must be set up prior to the clock pulse's rising edge and must not be changed before the falling. Otherwise , result will ambiguous.
The three basic types of pulse-triggered flip-flops are S-R J-K and D.their logic symbols are shown below. notice that do not have the dynamic input indicator at the clock input but have postponed output symbols at the outputs
The truth tables for the above pulse-triggered flip-flops are all the same as that for the edge-triggered flip-flops except for the way they are clocked. these flip-flops are also called master-slave flip-flops simply because their internal construction are divided into two sections . the slave section is basically the same as the master section except that it is
clock on the inverted clock pulse and is controlled by the outputs of the master section rather than by the external inputs . the logic diagram for basic master-slave S-R flip-flop is shown below.
Operating Characteristics
The Operating characteristics mentioned here apply to all flip-flops regardless of the particular from of the circuit. they are typically found in data sheets for integrated circuits. they specify the performance . operating requirements, and operating limitations of the circuit. propagation delay time-is the interval of time required after an input signal has been applied for the resulting output change to occur.
Set-Up time-is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and k , or S and R, or D )prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked in to the flip-flop.
Hold time -is the minimum interval required for the logic levels to remain on the inputs after the triggered edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
Maximum clock frequency-is the highest rate that a flip-flop can be reliably triggered
Power dissipation-is the total power consumption of the device.
Pulse widths-are the minimum pulse widths specified by the manufacture for the Clock, SET and CLEAR inputs.
Latch
Latch is a circuit used to latch some signal information. it has two status conditions:
- Latch open
- Latch closed
RS NAND Latch
the circuit shown below is a basic NAND latch. the inputs are generally designated "s" and "r" for "set" and "reset" respectively . because the NAND inputs must normally be logic 1 to latching action, inputs are considered to be invertered in this circuit. the outputs of any single-bit latch or memory are traditionally designated Q and Q', in a commercial latch circuit, either or both of these may be available for use by other circuits. in any case, the circuit itself is: for the NAND latch circuit, both inputs should normally be at a logic 1 level. changing an input to a logic 0 level will force that output to a logic 1. the same logic 1 will also be applied to the second input of the other NAND gate, allowing that output to fall to a logic 0 level. this in turn feeds back to the second input of the original gate, forcing its output to remain at logic1.
applying another logic 0 input to the same gate will have no further effect on this circuit. however, applying a logic 0 to the other gate will cause the same reaction in the other direction, thus changing the state of latch circuit the other way.
RS NOR Latch
While most of our demonstration circuits use NAND gates, the same functions can also be performed using NOR gates. A few adjustments must be made to allow for the difference in the logic function, but the logic involved is quite similar. the circuit shown below is a basic NOR latch. the inputs are generally designated "s" and "r" for "set" and "reset" respectively. because the NOR inputs must normally be logic 0 to avoid overriding the latchingaction, the inputs are not inverter in this circuit.
The NOR -based latch circuit is :
For the NOR latch circuit, both inputs should normally be at a logic 0 level. changing an input to a logic 1 level will force that output to a logic same logic 0 will also be applied to the second input of the other NOR gate, allowing that output to rise to a logic 1 level. this in turn feeds back to the second input of the original gate, forcing its output to remain at logic 0 even after the external input is removed. applying another logic 1 input to the same gate will have no further effect on this circuit. however, applying a logic 1 to the other gate will cause the same reaction in the other direction, thus changing the state of the latch circuit the other way .
one problem with the basic RS NOR latch is that the input signals drive their respective outputs to a logic 0, rather than to a logic 1. thus , the S input signal is applied to the gate that produces the Q ' output, while the R input signal is applied to the gate that produces the Q output. the circuit works fine, but this reversal of inputs can be confusing when you first try to deal with NOR-BASED CIRCUIT.
one problem with the basic RS NOR latch is that the input signals drive their respective outputs to a logic 0, rather than to a logic 1. thus , the S input signal is applied to the gate that produces the Q ' output, while the R input signal is applied to the gate that produces the Q output. the circuit works fine, but this reversal of inputs can be confusing when you first try to deal with NOR-BASED CIRCUIT.
D Latch
ONE very useful variation on the RS latch circuit is the data latch, or D latch as it is generally called. As shown in the logic diagram below, the D latch is constructed by using the inverted S input as the R input signal. the single remaining input is designated "D" to distinguish its operation from other types of latches. it makes no difference the R input signal is effectively clocked twice, since the CLK signal will either allow the signals to pass both gates or it will not.
In the D latch , when the CLK input is logic 1, the Q output will always reflect the logic level present at the D input, no matter how that changes. when the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch, for use by whatever other circuits may need this signal. because the signal D input is also inverted to provide the signal to reset the latch, this latch circuit cannot experience a "race" condition caused by all inputs being at logic 1 simultaneously. therefore the D latch circuit can be safely used in any circuit.
Counter
The counter is a circuit with a set of flip-flops which counts the number of pulses given at the clock input. At any time the number of pulse recieved is shown in the counter output, the output pattern in the flip-flops in different stages. the number of flip-flops used and how they arte connected determine the number of state and the sequence of the states.that the counter goes through in each complete cycle.
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